This application is based upon and claims priority from prior French Patent Application No. 0100418, filed on Jan. 12, 2001, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The invention relates to integrated circuits, and more particularly to dynamic random access memory cells of the DRAM (Dynamic Random Access Memory) type.
2. Description of the Prior Art
A memory cell of the DRAM type must be as small as possible for the sake of density. It consists of an access transistor controlling the charging or the discharging of a capacitor. This capacitor must, on the one hand, have a maximum capacitance and, on the other hand, occupy a minimum surface. Currently, the capacitor is made either in the silicon substrate or in the upper interconnect layers of the integrated circuit.
In the first case, the capacitor is located at the side of the access transistor. In the second case, the capacitor occupies a large volume above the transistor, a volume that cannot be used to make interconnections in the integrated circuit.
In both cases, the density of the memory cell, that is to say its overall size, is affected thereby.
Moreover, processes for fabricating semiconductor components may destroy the crystalline continuity of the surface of part of the initial single-crystal semiconductor substrate. This is especially the case when producing a trench. At the position of the trench, the semiconductor substrate has a different material without any crystalline structure. Consequently, the surface of that part of the substrate which is occupied by the trench cannot be used to produce semiconductor devices.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
A main aim of the invention is to provide a solution to the problems discussed above.
One aim of the invention is to produce a single-crystal substrate allowing the subsequent formation of a silicon epitaxial layer that is free of crystal defects and in which the transistor of the memory cell will be produced.
Another aim of the invention is to propose a semiconductor device operating as a memory cell of the DRAM type, and having a minimum overall size.
The invention therefore proposes a process for fabricating an integrated circuit comprising a semiconductor substrate supporting a memory cell of the DRAM type having an access transistor and a storage capacitor. According to a general characteristic of the invention,
a) an initial single-crystal substrate having locally a capacitive trench containing a polycrystalline fill material emerging at the surface of the initial substrate and forming a discontinuity in the crystal lattice is prepared;
b) the initial substrate is recessed at the trench;
c) the single-crystal lattice of the substrate around the periphery of the recess and the emergent part of the polycrystalline material for filling the trench are amorphized locally and so as to be self-aligned with respect to the trench;
d) a layer of amorphous material having the same chemical composition as that of the initial substrate is deposited on the structure obtained in the previous step;
e) the structure obtained in the previous step is thermally annealed in order to recrystallize the amorphous material so as to be continuous with the single-crystal lattice of the initial substrate;
f) an upper substrate layer, in and on which the access transistor is made, is grown by epitaxy, the capacitive trench forming the storage capacitor being in contact with one of the source and drain regions of the transistor.
According to one implementation mode, the process comprises, prior or subsequent to step e), a surface planarization step, for example a chemical-mechanical polishing operation.
According to one implementation mode, the amorphization step comprises ion implantation localized around the recess by means of a masking operation.
According to one implementation mode, in step a), a first layer of a first material and a second layer of a second material are deposited in succession on the initial substrate, then a trench is etched, which is filled with a fill material, and
in step b), the first layer and an upper portion of the trench fill material are selectively etched with respect to the second layer so as to form lateral cavities and the recess at the crystal discontinuity, and the second layer is removed.
In step a), the filling of the trench advantageously comprises the following steps:
the walls of the trench are lined with oxide by thermal oxidation;
highly doped polycrystalline silicon is deposited in the trench so as to fill it;
the polycrystalline silicon deposited previously is etched so that the fill level of the trench is below the surface of the initial substrate.
The subject of the invention is also an integrated circuit obtained by the fabrication process as defined above and comprising a semiconductor substrate supporting a memory cell of the DRAM type comprising an access transistor and a storage capacitor.
Thus, the substrate includes at least one capacitive trench buried beneath the transistor and forming the storage capacitor, the capacitive trench being in contact with one of the source and drain regions of the transistor.
In other words, the memory cell thus obtained according to the invention is a transistor with a capacitor of the buried-trench type, the trench being located not beside the transistor but beneath the transistor. The footprint is therefore reduced. The first electrode of the capacitor is the substrate and the second electrode is a conductor filling the trench. This capacitor is located beneath a diffusion region (drain or source) of the access transistor and is connected to this diffusion region by direct contact between the internal electrode of the capacitor and this diffusion region.
The substrate is, for example, formed from silicon and the capacitive trench includes a doped-silicon internal region partially surrounded by an isolating wall which laterally separates the internal region from the substrate and is surmounted by a doped-silicon upper region, this upper region being in contact with the source or drain region of the transistor.
According to one embodiment, the substrate includes a highly doped lower part of p-type conductivity, preferably with a dopant concentration of greater than 1018 at/cm3, for example 1019 at/cm3, and an upper part of p-type conductivity, but less doped than the lower part. The internal region and the upper region of the capacitive trench have an n-type conductivity and the source and drain regions of the transistor also have an n-type conductivity.